1. Field of the Invention
The present invention relates to a semiconductor device, particularly to a layout of a power field effect transistor (FET).
2. Description of the Related Art
In a conventional semiconductor device, a high power FET and a medium power FET are respectively fabricated as a single-chip discrete device. These are connected together on a circuit substrate. Gate widths of these FETs vary based on utilized frequencies and power supplies. For example, in 900 MHz cellar phones, gate widths of the high power FETs are about 10 mm and gate widths of the medium power FETs are about 3 mm. A gate width usually differs between respective FETs FIG. 4(a) is a plan view showing a high power FET in accordance with the prior art.
FIG. 4(b) is a plane view showing a medium power FET having the same gate width, in accordance with the prior art.
Referring to FIG. 4(a), t-he high power FET comprises a plurality of source pads S41-S44, a plurality of gate pads G41-G43, a plurality of drain pads D41-D44, and a plurality of gates F41, formed on a semiconductor chip C41. An array has the source pads S41-S44 and the gate pads G41-G43 alternately arranged, and they are separated from the drain pads D41-D44, by the gates F41. A gate width of the gates F41 is set to L41.
Referring to FIG. 4(b), the medium power FET comprises a plurality of source pads S47, S48, a gate pad G45, a plurality of drain pads D47, D48, and a plurality of gates F42, formed on a semiconductor chip C43. An array has the source pads S47, S48 and the gate pad G45 arranged alternately, and they are separated from the drain pads D47, D48, by the gates F42. A gate width of the gates F42 is set to L42, which is shorter than L41.
Since the high power FET and the medium power FET, in accordance with the prior art, have respectively different gate widths, a pinch off voltage (Vp) of each O-FET is also respectively different when an implantation condition and a recess condition for forming the conducting layers of the FETs are the same.